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Dr. Rahul Panat's Advanced Manufacturing Lab

Research Interests

 

The lab has moved to Carnegie Mellon University. Please visit:

https://www.meche.engineering.cmu.edu/faculty/panat.html 
https://advancedmanufacturing.us/

 

AML is interested in solving fundamental and applied problems in the areas of printed and flexible microelectronics manufacturing and Li-ion batteries. These areas are highly relevant to realize devices and systems for wearable and Internet of Things (IoT) segments. Examples include smart contact lens, wearable electronic clothing, robotic skins, bio-patches etc.

Several fundamental breakthroughs have been achieved this year, including,

a) First demonstration of stretching of a metal sheet to 100% linear strain without failure (e.g. minimal resistivity increase after about 30% strain)- see news. A patent has been filed. See link to the paper.

b) Discovery of in-situ cured microscale metal-dielectric structures for 3-D antennas and passives. Two patents have been filed. See link to the paper.

c) Several key findings in the area of Aerosol Jet micro-additive printing of batteries (one patent filed) and battery degradation (see the latest paper). We are currently in the ‘discovery’ phase and will add the results when appropriate.

Challenges: The manufacturing problems in this area are involved due to the demanding functional requirements and the length scales involved. For example, logic/memory elements in the IC chip (10nm-to-few microns), high density substrate (5-100micron), and board (100micron – few mm) form the wearable device with the feature scale spanning 6 orders of magnitude. The wearable system also needs to accommodate passives, energy sources, sensors, antenna, and other components. The sensors can either be integrated with the IC chip or can be separate entities on the board. The high density substrate has interconnect lines on polymer at line/space of ~10/10 micron and are a few microns thick. The board interconnect lines can be 10s of μm in width and 10s of μm in thickness. The metallization within Si has Cu lines at 100nm length scale. Of course, the transistors are at ~10nm length scale. The first level interconnects (typically alloys of Sn-Cu or Sn-Cu-Ag) are at about 50micron pitch and need an underfill polymer that helps chip wither the different CTE with respect to the board as well as the high density substrate

Links to Current Projects:

  1. Micro-Additive Manufacturing for sensors, antennas, and energy harvesting
  2. Flexible/Stretchable Electronics
  3. Li-ion Batteries
  4. Thermodynamics